Programmable Logic Devices (PLDs) are widely used in the field of digital circuitry and are typically comprised of an array of driver circuits and AND-arrays that can be re-configured to perform many different Boolean equations. To implement a particular Boolean equation, a PLD typically receives several input signals. Each input signal is fed into one or more sets of driver circuits and AND-arrays within the PLD. The driver circuits and AND-arrays respond to the input signals and generate one or more output signals.
One of the ways in which driver circuits and AND-arrays can be re-configured is into a truth-and-complement circuit. A truth-and-complement circuit either generates an output signal equal to an input signal or generates an output signal equal to a complement of the input signal. For example, if signal "A" is input into the driver circuits, then the truth-and-complement circuit may be programmed to output either A, or its complement, A. The output signal is transmitted on a bit-line.
A sense amplifier detects the output signal and boosts it before passing it to another portion of the PLD. The sense amplifier either outputs a logic "1" or a logic "0" depending upon the voltage it detects on the bit-line. The difference between a first voltage on the bit-line which causes the sense amplifier to generate a logic "1" and a second voltage on the bit-line which causes the sense amplifier to generate a logic "0" is called a "voltage differential" of the sense amplifier.
The speed of a sense amplifier is inversely proportional to the voltage differential and necessarily affects the PLD's maximum speed. For instance, a sense amplifier with a large voltage differential requires more time to accumulate charge before it switches from logic "0" to logic "1." As a result, the sense amplifier operates more slowly, and therefore the operational speed of the PLD is reduced. Conversely, if the sense amplifier has a small voltage differential, the sense amplifier charges and discharges more quickly and thus enables the PLD to operate at a faster speed. Thus, it is very desirable that the voltage differential be as small as possible.
The size of the required voltage differential depends upon a noise voltage present on the bit-line. The voltage differential must be greater than the noise voltage on the bit-line so that the sense amplifier does not misinterpret the noise voltage as the input signal. Thus, the noise voltage limits the PLD's maximum speed.
One of the contributors to the noise voltage on the bit-line is the driver circuit. Present driver circuits add to the noise voltage on the bit-line due their path delay differences between their truth output and complement output. The truth output is a line which transmits the input signal without any logic modifications. The complement output is a line which transmits the complement of the input signal. The path delay difference is created when an extra inverter is placed within one of the paths, thereby causing the complement of the input signal to be output at a slightly later time than the signal itself. Since both the truth and the complement outputs are coupled to the bit-line via undesirable parasitic capacitances, even when the AND-arrays are not programmed to connect either signal to the bit-line, the signals add to the noise voltage on the bit-line.
Therefore, what is needed is an improved truth-and-complement circuit which generates a smaller noise voltage on the bit-line.